Compute-in-Memory: SRAM, DRAM, and the Location of Computation
SourcesSurvey §3, §3.2 and §6.2; corpus extends the case pool beyond the three surveyed CIM families.
4.9.4The Differing Limits of SRAM Capacity, DRAM Internal Bandwidth, and Compute Throughput#
4.9.5Mapping Differences Between GEMV/Small-Batch and High-Reuse GEMM#
4.9.6Corpus Extension: Analog Flash Compute in Mythic#
4.9.8Terminological Boundaries Among CIM, PNM, and 3D Logic–Memory Integration#