AI Architecture & Systems

Core Taxonomy: Four Classes of AI Accelerator Architecture

SourcesSurvey §3, Table 1 and Fig. 4.

4.3.1GPU: SIMT Architecture and Dedicated Tensor/Matrix Units#

4.3.2NPU: Matrix/Vector/Scalar Engines Around a Shared Scratchpad#

4.3.3Spatial Dataflow: Computation Graphs Mapped onto Distributed Compute, Memory, and Communication Resources#

4.3.4Compute-in-Memory: Arithmetic Units Inside or Adjacent to Memory Arrays#

4.3.5Three Subclasses of Spatial Dataflow: PE Array, Reconfigurable, Functional-Slice#

4.3.6Systolic Execution, Memory Technology, and Their Non-One-to-One Relation to Architecture Class#

4.3.7Primary Categories, Generational Differences, and Hybrid Implementations#