Spatial Dataflow I: PE Arrays and Distributed Local Memory

SourcesSurvey §3, Fig. 4(c) and Table 2; additional PE-array and manycore cases follow the corpus labels.

4.6.1Tenstorrent: Tensix, RISC-V Control, and NoC Data Movement#

4.6.2Meta MTIA: PE Grid and Model–Chip Co-Design#

4.6.3Graphcore IPU: MIMD Tiles, Local SRAM, and BSP#

4.6.4Tesla Dojo: Tile Processor and Hierarchical Communication#

4.6.5Cerebras: Wafer-Scale PE Mesh and Data-Triggered Execution#

4.6.6Boundaries Among On-Chip PE Mesh, In-Package Interconnect, and Inter-Accelerator Networks#

4.6.7Corpus Extensions: IBM Spyre and Enflame#

4.6.8Corpus Extensions: MN-Core, Esperanto, and PEZY#