Programming Models: Understanding Hardware Constraints Through Software Layers

SourcesCorpus software-layer schema and the per-chip layer mappings; survey §3 supplies the architectural context.

4.12.1Framework Integration, Compiler/IR, and Operator Library#

4.12.2Kernel Library, Runtime, Driver/Firmware, and Assembler/ISA#

4.12.3Communication Libraries and Compiler-Built-In Communication#

4.12.4Thread/Warp, Tensor Tile, PE/Vertex, and Static Streaming Programming#

4.12.5Kernel-Launched, Graph-Executed, and Data-Triggered Models#

4.12.6Registers, Scratchpad, Distributed SRAM, and Explicit Data Movement#

4.12.7Standalone Libraries, Compiler-Merged Layers, Undisclosed Interfaces, and Historical Interfaces#

4.12.8The Causal Chain from Hardware Resources to Software Responsibility to Programming Model#