Cross-Generation Comparison: Memory Hierarchy and Scale-Up Fabric

SourcesSurvey §5.3, Table 4 and Fig. 15; corpus numerical discrepancies remain separately documented in the linked records.

4.27.1HBM Capacity: Die Density, Stack Height, and Stack Count#

4.27.2HBM Bandwidth: Signaling Rate, Interface Width, and Stack Count#

4.27.3Shared Cache, Scratchpad, and On-Chip Reuse Capacity#

4.27.4Chiplet Packaging and Memory PHY/Controller Integration#

4.27.5GPU Fabric: Direct Connection, Switched Node, and Rack Domain#

4.27.6Neuron: Torus, Inter-Instance Ring, and Switched Fabric#

4.27.7TPU: Design Trade-offs Among Torus, OCS, and Boardfly#

4.27.8Joint Comparison of Device Memory, Platform Topology, and Cross-Generation Data Conventions#