AI Architecture & Systems
1
Microarchitecture
2
Kernel
3
Compiler
4
Architecture
5
System
6
Algorithms
Architecture
/
§4.25
Specialized Accelerator Generations: Workload Positioning and Hardware–Software Co-Design
Sources
Survey §2.3 and §5;
TPU
,
Neuron
,
MTIA
and
Maia
corpus records.
4.25.1
TPU v1 → v2/v3: Bridging Inference and Training Designs
#
4.25.2
TPU v4/v5e/v5p/v6e/v7: Compute, Memory, and Pod Evolution
#
4.25.3
TPU 8t/8i: Workload Positioning and Disclosure Boundaries in the Survey
#
4.25.4
AWS Inferentia/Trainium: NeuronCore and Multi-Engine Evolution
#
4.25.5
Trn1/Trn2: Intra-Instance Torus and Inter-UltraServer Connection
#
4.25.6
Trn3: Switched Fabric Evolution in the Survey
#
4.25.7
MTIA/Maia: Shifts Across Recommendation, Generative AI, and Inference Workloads
#
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4.24 GPU Generational Evolution: Compute, Data Supply, and Cooperation Scope
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4.26 Cross-Generation Comparison: Numerical Formats, Structured Sparsity, and Peak Conventions