AI Architecture & Systems
1
Microarchitecture
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Kernel
3
Compiler
4
Architecture
5
System
6
Algorithms
Microarchitecture
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§1.6
Dataflow and Data Reuse
1.6.1
Temporal Reuse and Spatial Reuse
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1.6.2
Weight-Stationary, Output-Stationary, and Input-Stationary
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1.6.3
Row-Stationary and Hybrid Dataflow
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1.6.4
Loop Nest, Loop Order, and Reuse Distance
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1.6.5
Local Reuse, Cross-PE Reuse, and Cross-Tile Reuse
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1.6.6
Compute, Storage, and Communication Trade-offs in Dataflow
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1.5 Systolic Array Design
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1.7 TPU v1 Case Study: From Systolic Array to GEMM Execution