Hierarchical GEMM Mapping and Tiling

1.14.1M/N/K Dimensions and Loop Nest Mapping#

1.14.2DRAM Tile, SRAM Tile, and Register Tile#

1.14.3Spatial Unrolling, Temporal Reuse, and Array Mapping#

1.14.4Residency Strategies for Weights, Activations, and Partial Sums#

1.14.5Tile Size, Memory Capacity, and Port Bandwidth Constraints#

1.14.6Mapping Differences Among Large, Tall-Skinny, and Small Matrices#

1.14.7The Complete Dataflow from DRAM to PE and Back#