AI Architecture & Systems
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Microarchitecture
2
Kernel
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Compiler
4
Architecture
5
System
6
Algorithms
Microarchitecture
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§1.13
Roofline and Performance Upper Bounds
1.13.1
Arithmetic Intensity and Data Traffic at Each Memory Boundary
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1.13.2
Compute Roof, Memory Roof, and Ridge Point
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1.13.3
Peak Roofline and Empirical Roofline
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1.13.4
Hierarchical Register/SRAM/DRAM Roofline
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1.13.5
Batch Size, Matrix Shape, and Reuse in GEMM/GEMV
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1.13.6
Beyond the Bandwidth Bound: Launch Latency, Synchronization, Dependencies, and Utilization Limits
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1.13.7
Data-Movement Energy and the Energy Roofline
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1.12 On-Chip Interconnect and Synchronization
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1.14 Hierarchical GEMM Mapping and Tiling