AI Architecture & Systems
1
Microarchitecture
2
Kernel
3
Compiler
4
Architecture
5
System
6
Algorithms
Microarchitecture
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§1.11
Data Movement and Asynchronous Execution
1.11.1
Load/Store Unit and Address Generators
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1.11.2
DMA, Descriptors, and Asynchronous Copy
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1.11.3
Gather/Scatter and Non-Contiguous Data Movement
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1.11.4
Memory-Level Parallelism and Outstanding Requests
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1.11.5
Producer–Consumer Pipelines and Double Buffering
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1.11.6
Barrier, Fence, Semaphore, and Data Visibility
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1.11.7
Overlap Among Compute, Data Movement, and the Memory Hierarchy
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1.10 DRAM and External Memory Interfaces
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1.12 On-Chip Interconnect and Synchronization