AI Architecture & Systems

Spatial Dataflow Compilation: Graph Mapping, Memory Placement, and Communication Scheduling

3.17.1Tenstorrent: TT-Forge/TT-XLA → TT-MLIR → TT-NN/TT-Metalium#

3.17.2Graphcore Poplar: Tile Assignment, Codelets, and BSP Exchange#

3.17.3Cerebras: Graph Compilation, CSL Tasks, and Layer-Pipelined/Weight-Streaming Execution#

3.17.4SambaFlow (SN40L-Era): PCU/PMU Placement, Routing, and Meta-Pipelines#

3.17.5Groq: Functional-Slice Placement, Cycle Scheduling, and Link Scheduling#

3.17.6Temporal Reuse, Spatial Unrolling, SRAM Allocation, and Routing Resource Constraints#

3.17.7Trade-offs Between Compile-Time Conflict Elimination and Runtime Scheduling#